Home
News
Problems
FAQ
Registration
Winners
History
Contact
Contest Problems
Problem A
Hardware Trojan Detection on Gate Level Netlist
*last update 03/07
(Cadence Design Systems, Inc.)
Problem B
Power and Timing Optimization Using Multibit Flip-Flop
*last update 04/23
(
Q&A
)
*last update 04/24
(Synopsys, Inc.)
Problem C
Incremental Placement Optimization Beyond Detailed Placement:Simultaneous Gate Sizing, Buffering, and Cell Relocation
*last update 04/25
(
Q&A
)
*last update 04/07
(NVIDIA Research)
Please
read FAQs
for more information, or
contact us
for any further question.
Copyright © 2025 CAD Contest. All Rights Reserved.